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In this paper, we considered four different interference suppression algorithms in a single-input multiple-output receiver, where channel diversity is intentionally introduced to improve interference tolerance. Matched filter (MF), zero forcing (ZF), blind interference estimation and suppression (BIES) which we had previously proposed, and minimum variance distortionless response (MVDR) are considered. Each algorithm is introduced, and the recombining weight vectors are derived. A loss function is defined to compare the performance of the algorithms, showing superior performance of MVDR, and confirming that the proposed BIES algorithm achieves a comparable performance to MVDR. The four algorithms are then applied on measured data from a chip that was designed and fabricated in \qty{45}{\nm} RF SOI process for the frequency range of 1.2-2.4GHz. Measurement results are compared for the four algorithms, confirming significant improvement by using MVDR, BIES, and ZF compared to MF for large interference, as predicted by the derived equations, and showing adaptability of MVDR and BIES to small levels of interference as opposed to ZF. 

This paper presents a novel system architecture to suppress in-band artifacts (IBAs) generated from out-of-band (OOB) interferers, including reciprocal mixing by the local oscillator's (LO) spurs and phase noise (PN), third-order intermodulation (IM3) artifacts, and harmonic down-conversion (HDC) artifacts. Theory and design procedure are explained, and measurement results from a prototype taped out in 45nm RF SOI process are presented. The receiver was designed for the frequency range of 1.2-2.4GHz and achieved a noise figure (NF) of 3.1-6.2dB, blocker -1dB compression point (B1dB) of -10.3Bm, and OOB third-order input-referred intercept point (IIP3) of 9.3dBm on average, before artifact suppression. Measurements were performed on 16-quadrature amplitude modulated (16QAM) signals with modulated and unmodulated OOB interferers to show artifact suppression for various kinds of IBA. For each IBA, artifact suppression performance was assessed across frequency and interferer power. Interference tolerance improvement of up to 38dB was achieved. Additionally, reconstruction of the artifacts for the cases of spur and HDC was demonstrated, showing simultaneous recovery of two signals, providing a form of carrier aggregation. 

This paper presents a novel technique for suppression of in-band artifacts from out-of-band (OOB) interference in widely tunable RF receivers. The technique employs a multi-tap inductor-capacitor network (LCN) to generate diversity in gain and phase between taps across the targeted frequency range. Using this network to feed a bank of identical receivers sharing a single local oscillator (LO) allows multiple kinds of interferer artifact to be suppressed. Here we considered spur-induced and phase noise-induced artifacts. In each case, the resulting artifacts are linearly separable from signal when the outputs of the sub-receivers are recombined. AC and transient simulations were first performed to show feasibility of the proposed approach. A prototype was implemented in 45nm CMOS which confirmed the validity of the synthetic diversity (SD) approach for suppressing interferer artifacts, showing a maximum lowering in EVM and BER of 38% and 60% respectively. 

Here we present a combined RF hardware/DSP technique to synthesize effective channel diversity in single-antenna wireless systems. This allows digital suppression of out-of-band interference artifacts in widely tunable wireless receivers with one or more antennas, including artifacts from LO phase noise. A passive inductor-capacitor (LC) network provides gain and phase diversity between channels and across frequency. Since amplitude and phase of in-band artifacts are set by the amplitude and phase of the out-of-band interference that generates them, they can be suppressed in DSP without knowledge about the interferer itself. The feasibility of this approach is demonstrated mathematically, with numerical system simulations, and full circuit simulation.